Now we can proceed to studying specific types of digital storage devices. To start, I want to
explore some of the technologies which do not require any moving parts. These are not necessarily
the newest technologies, as one might suspect, although they will most likely replace
moving-part technologies in the future.
A very simple type of electronic memory is the bistable multivibrator. Capable of storing
a single bit of data, it is volatile (requiring power to maintain its memory) and very fast. The
D-latch is probably the simplest implementation of a bistable multivibrator for memory usage,
the D input serving as the data ”write” input, the Q output serving as the ”read” output, and
the enable input serving as the read/write control line:
explore some of the technologies which do not require any moving parts. These are not necessarily
the newest technologies, as one might suspect, although they will most likely replace
moving-part technologies in the future.
A very simple type of electronic memory is the bistable multivibrator. Capable of storing
a single bit of data, it is volatile (requiring power to maintain its memory) and very fast. The
D-latch is probably the simplest implementation of a bistable multivibrator for memory usage,
the D input serving as the data ”write” input, the Q output serving as the ”read” output, and
the enable input serving as the read/write control line:
If we desire more than one bit’s worth of storage (and we probably do), we’ll have to have
many latches arranged in some kind of an array where we can selectively address which one
(or which set) we’re reading from or writing to. Using a pair of tristate buffers, we can connect
both the data write input and the data read output to a common data bus line, and enable
those buffers to either connect the Q output to the data line (READ), connect the D input to
the data line (WRITE), or keep both buffers in the High-Z state to disconnect D and Q from the
data line (unaddressed mode). One memory ”cell” would look like this, internally:
When the address enable input is 0, both tristate buffers will be placed in high-Z mode, and
the latch will be disconnected from the data input/output (bus) line. Only when the address
enable input is active (1) will the latch be connected to the data bus. Every latch circuit, of
course, will be enabled with a different ”address enable” (AE) input line, which will come from
a 1-of-n output decoder:
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